The present invention relates to a capacitor for semiconductor memory device and a method of manufacturing the same, and more particularly to a capacitor for semiconductor memory device with a dielectric layer having low leakage current and high dielectric constant and method of manufacturing the same.
Along with the recent progress in the semiconductor manufacturing technology, the demand for memory device has increased dramatically. Consequently, a memory device having higher capacitance per small dimension is required. Capacitance of the capacitor is increased by using an insulator having high dielectric constant or enlarging the surface area of a lower electrode. Those conventional capacitors have used Ta2O5 layer having a dielectric constant higher than that of nitride-oxide(NO) layer as a dielectric, thereby forming the lower electrode having 3-Dimensional structure.
FIG. 1 is a cross-sectional view showing a capacitor in a conventional semiconductor memory device. Referring to FIG. 1, a gate electrode 13 including a gate insulating layer 12 at a lower portion thereof is formed by a known technique on an upper part of a semiconductor substrate 10 which a field oxide layer 11 is formed at a selected portion thereof. A junction region 14 is formed on the semiconductor substrate 10 at both sides of the gate electrode 13, thereby forming an MOS transistor. A first interlevel insulating layer 16 and a second interlevel insulating layer 18 are formed on the upper part of the semiconductor substrate 10 on which the MOS transistor has been formed. A storage-node contact hole h is formed in the first and the second interlevel insulating layers 16 and 18 so that the junction region 14 is exposed. A cylinder type lower electrode 20 is formed by a known technology in a storage-node contact hole h to be contact with the exposed junction region 14. A hemi-Spherical grain(HSG) layer 21 is formed on the surface of the lower electrode 20 in order to increase the surface area of the lower substrate 20. A Ta2O5 layer 23 is formed on the surface of the HSG layer 21. At this time, the Ta2O5 layer 23 is formed as follows. First, a surface of the HSG layer 21 is cleaned before the Ta2O5 layer 23 is formed, and then the RTN(rapid thermal nitridation) process is performed ex situ, thereby forming a silicon-nitride layer 22 on the surface of the HSG layer 21. Next, a first Ta2O5 layer is formed at a temperature of approximately 400xcx9c450xc2x0 C. to thickness of 53xcx9c57 xc3x85. Afterward, an annealing process is performed at low temperature, and then a second Ta2O5 layer is formed to the same thickness and by the same process as in the first Ta2O5 layer. Annealing processes at low temperature and at high temperature are continued in series, thereby forming a single Ta2O5 layer 23. An upper electrode 24 is deposited on upper parts of the Ta2O5 layer 23 and the second interlevel insulating layer 18, thereby completing the formation of a capacitor.
However, the conventional capacitor formed according to the above method using the Ta2O5 layer as a dielectric layer has the following problems.
First, a difference in the composition rate of Ta and O is generated since the general Ta2O5 layer has unstable stoichiometry. As a result, substitutional Ta atoms, i.e. vacancy atoms, are generated in the thin film. Since those vacancy atoms are oxygen vacancies, leakage current is generated. The amount of vacancy atoms can be controlled depending on the contents and the bond strength of components in the Ta2O5 layer; however, it is difficult to eliminate them completely.
In order to stabilize the unstable stoichiometry of the Ta2O5 layer, the Ta2O5 layer is oxidized so as to remove the substitutional Ta atoms in the Ta2O5 layer. However, when the Ta2O5 layer is oxidized, the following problems occur. That is, the Ta2O5 layer has high oxide reaction with an upper electrode and a lower electrode formed of polysilicon or TiN and so forth. Therefore, in an oxide process to oxidize the substitutional Ta atoms, an oxide layer having a low dielectric constant is formed at an interface since the Ta2O5 layer and the upper electrode or the lower electrode react to one another, and oxygen moves to the interface between the Ta2O5 layer and the lower electrode, thereby deteriorating the homogeneity of the interface.
Further, since an organic substance such as Ta(OC2H5)5 used as a precursor has a large amount of carbon components, impurities such as carbon atoms C, carbon compounds(CH4, C2H4) and H2O result in the Ta2O5 layer. These impurities increase leakage current in the capacitor and degrade the dielectric characteristics of the Ta2O5 layer. Accordingly, a capacitor having a large capacitance is difficult to obtain.
Moreover, using the Ta2O5 layer as a dielectric layer increases extra ex-situ steps, i.e. one before formation of Ta2O5 layer and one after the cleaning step. Also, two steps of Ta2O5 deposition should be applied to the formation of the Ta2O5 layer, and two thermal processes at low and high temperatures are performed after the Ta2O5 layer has been formed. Therefore, forming a dielectric layer with Ta2O5 using the conventional method is cumbersome.
Accordingly, it is one object of the present invention to provide a capacitor for semiconductor device capable of obtaining a great capacitance by providing a dielectric layer having low leakage current and high dielectric constant.
Furthermore, the other object of the present invention is to provide a method of manufacturing capacitor for semiconductor device capable of simplifying manufacturing process thereof.
According to one embodiment of the present invention, a capacitor on a semiconductor substrate includes: a lower electrode; a dielectric layer formed on the lower electrode; and an upper electrode formed on the upper part of the dielectric layer, wherein the dielectric layer is an amorphous TaON layer.
In another aspect of the present invention, the present invention provides a method of forming a capacitor for semiconductor memory device including the steps of: forming a lower electrode on the semiconductor substrate; depositing an amorphous TaON layer as a dielectric layer on the upper part of the lower electrode; thermal-treating the amorphous TaON layer in a range of maintaining the amorphous state; and forming an upper electrode on the upper part of the TaON layer.
Still another aspect of the present invention, the present invention provides a method of forming a capacitor for semiconductor memory device including the steps of: forming a lower electrode on the semiconductor substrate; surface-treating the lower electrode; depositing an amorphous TaON layer as a dielectric layer on the upper part of the lower electrode; thermal-treating the amorphous TaON layer in a range of maintaining the amorphous state; and forming an upper electrode on the upper part of the TaON layer, wherein the amorphous TaON layer is formed by a wafer surface chemical reaction of a Ta chemical vapor obtained from a precursor, O2 gas and NH3 gas with pressure of 0.1 to 100 Torr at a temperature of 300 to 600xc2x0 C. in an LPCVD chamber.